A known prior art fabrication process, illustrated in FIGS. 1A and 1B, is a process for fabricating a plurality of semiconductor-on-insulator structures 20, the insulator being a layer 22 of silicon dioxide of thickness smaller than 50 nm, the fabrication process comprising a step of heat treating the plurality of structures 20, which heat treatment step is designed to partially dissolve the silicon dioxide layer 22.
In this regard, a person skilled in the art will find a technical description of the dissolution of a silicon dioxide layer in the following articles by Kononchuk: Kononchuk et al., “Novel trends in SOI technology for CMOS applications,” Solid State Phenomena, Vols. 156-158 (2010) pp. 69-76, and Kononchuk et al., “Internal Dissolution of Buried Oxide in SOI Wafers,” Solid State Phenomena, Vols. 131-133 (2008) pp. 113-118.
Each structure 20 comprises a semiconductor layer 23 placed on the silicon dioxide layer 22, the semiconductor layer 23 having a free surface S1.
The silicon dioxide layer 22 rests on a carrier substrate 21.
The carrier substrate 21 has a free side S4.
The heat treatment is designed to partially dissolve the buried silicon dioxide layer 22. It is generally carried out in an oven 10 containing a plurality of structures 20. As shown in FIG. 2, the structures 20 intended to be heat treated are stacked in the oven 10 so that the free surface S1 of the semiconductor layer 23 of each structure 20 faces the free side S4 of the carrier substrate 21 of the structure 20 above.
A non-oxidizing atmosphere is ensured by a flow of non-oxidizing gas injected into the oven 10 via an inlet 11 and pumped from the oven 10 via an outlet 12.
The main drawback of this heat treatment is that it degrades the thickness uniformity of the silicon dioxide layer 22 and of the semiconductor layer 23, as illustrated in FIG. 1B.
This drawback is not observed in an oven 10 containing a single structure 20. However, given the relatively long heat treatment times and for economic reasons, it is not envisageable from an industrial point of view to carry out such a process in an oven 10 containing only a single structure 20.
As shown in FIG. 1B, after the heat treatment, the thickness of the silicon dioxide layer 22 and the thickness of the semiconductor layer 23 are greater at the center of the structure 20 than at its edge. When the silicon dioxide layer 22 and the semiconductor layer 23 have a thickness greater than 50 nm and 80 nm, respectively, any degradation in the thickness of the layers does not pose a major problem.
However, certain applications require the silicon dioxide layer 22 to have a thickness smaller than 50 nm, in order to allow, for example, an electrical voltage to be applied to devices produced in or on the semiconductor layer 23. It is then necessary for the thickness of the silicon dioxide layer 22 to be very precisely controlled.
Moreover, fully depleted silicon-on-insulator (FDSOI) structures are particularly advantageous for the production of electronic components such as fully depleted metal oxide semiconductor (FDMOS) transistors, the channels of which are formed in or on the semiconductor layer 23.
Because of the extreme smallness of the thickness of the semiconductor layer 23, the threshold voltage of the transistor (usually denoted Vt), which depends on this thickness, is very sensitive to variations in the thickness of the semiconductor layer 23.
One object of the disclosure is, therefore, to provide a process for fabricating semiconductor-on-insulator structures allowing the thicknesses of the semiconductor and silicon dioxide layers 23, 22 to be controlled with precision.